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74heat score
+15 ▲net new, 7d
+45net new, 30d
#22 ▲22heat rank
99open 60+ days
Hiring timeline (26 weeks)
Opened (by posting date) Closed (tracked since 2026-10-16)
Salary bands
Chip / ASIC design
$188K–$232K med $212K · n=22
Bars show p25–p75 of posted US base pay; the tick is the median.
All roles: p25–p75 $185K–$225K, median $212K (69 postings).
Top functions
Top locations
Silicon Valley (South Bay) 86Tel Aviv 19Bangalore 14Taipei / Hsinchu 13Toronto 7Singapore 6
Recent signals
- 🔥Hiring surge · todayAstera Labs is on a hiring surge: 15 roles opened this week (vs 7 the week before)
See the 15 roles behind the signal
- Director ASIC Technical Program Management San Jose, California, United States
- Principal Digital Design Engineer San Jose, California, United States
- Teach Lead Physical Design Engineer Singapore, Singapore
- Principal Physical Design Engineer Singapore, Singapore
- Analog Mixed Signal Design Engineer Singapore, Singapore
- Tech Lead Analog Mixed-Signal IC Layout Engineer Singapore, Singapore
- Senior Analog Mixed-Signal IC Layout Engineer Singapore, Singapore
- Senior Manager, Global Safety & Security San Jose, California, United States
- Senior Manager, Global Environmental Health & Safety San Jose, California, United States
- Principal Mixed Analog Design Engineer Irvine, California, United States
- Principal NPI Supply Planner - PCBA Suzhou Qu, Gansu, China
- Principal Physical Design Engineer Ahmedabad, Gujarat, India
- Principal Physical Design CAD Engineer Haifa District, Israel
- System Validation manager Haifa District, Israel
- Principal NPI Planner Suzhou Qu, Gansu, China
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Hiring? Get your roles featured in the signals feed and role lists. $99 $29 per role / 30 days Founding employer price · 20 of 20 spots left
Get featuredSee the roles behind the signal
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Showing 20 of 78 recent roles. See all
Always hiring · 99 evergreen roles
Open 60+ days. Often standing roles companies keep open year-round.
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Showing 30 of 99. See all